1. Field of the Invention
This invention relates to semiconductor packaging technology, and more particularly, to a chip-on-chip (COC) based multi-chip module (MCM) with molded underfill and method of fabricating the same.
2. Description of Related Art
Multi-chip module (MCM) is a type of semiconductor package that is used to pack two or more semiconductor chips in one single package unit, so that one single package unit is capable of offering a manifold level of functionality or data storage capacity. Memory chips, such as flash memory chips, are typically packaged in this way so as to allow one single memory module to offer an increased data storage capacity.
A conventional method for fabricating a small-size multi-chip module is through the use of chip-on-chip (COC) technology, by which one semiconductor chip is arranged in an upside-down flip chip manner over the active surface of another chip and bonded to the same by means of an array of solder bumps. The COC technology has the benefit of allowing the finished package unit to have a reduced height.
One problem to the COC architecture, however, is that a flip-chip undergap would be undesirably left between the overlying chip and the underlying chip due to the existence of solder bumps therebetween. This flip-chip undergap, if not underfilled, would easily cause the two chips to suffer from fatigue cracking and electrical failure when the entire package structure is being subjected to high-temperature conditions. As a solution to this problem, it is an essential step in the fabrication of a COC-based multi-chip module to fill an underfill material, such as resin, into such the flip-chip undergap, so as to provide mechanical reinforcement to the two chips. The involved process step is customarily referred to as flip-chip underfill.
A conventional method for fabricating a COC-based multi-chip module is illustratively depicted in the following with reference to FIGS. 1A-1D.
Referring first to FIG. 1A, by this conventional method, the first step is to prepare a circuited substrate 100 and at least three semiconductor chips, including a first semiconductor chip 110, a second semiconductor chip 120, and a third semiconductor chip 130.
The circuited substrate 100 is a conventional and well-known substrate type for BGA application, which has a front surface 100a and a back surface 100b, and whose front surface 100a is used for mounting the chips 110, 120, 130, while the back surface 100b is used for the implantation of a ball grid array (shown later in FIG. 1D with the reference numeral 180).
The first semiconductor chip 110 has an active surface 110a and an inactive surface 110b, and whose inactive surface 110b is adhered to the front surface 100a of the circuited substrate 100 and whose active surface 110a is electrically coupled to the circuited substrate 100 by means of a plurality of bonding wires 111, such as gold wires.
The second semiconductor chip 120 has an active surface 120a and an inactive surface 120b, and whose active surface 120a is mechanically bonded and electrically coupled to the active surface 110a of the first semiconductor chip 110 through COC technology by means of an array of solder bumps 121. As the second semiconductor chip 120 is mounted in position over the first semiconductor chip 110, however, a flip-chip undergap 122 would be undesirably left therebetween due to the existence of the solder bumps 121.
The third semiconductor chip 130 has an active surface 130a and an inactive surface 130b, and whose active surface 130a is also mechanically bonded and electrically coupled to the active surface 110a of the first semiconductor chip 110 through COC technology by means of an array of solder bumps 131. As the third semiconductor chip 130 is mounted in position over the first semiconductor chip 110, however, a flip-chip undergap 132 would be undesirably left therebetween due to the existence of the solder bumps 131.
Referring further to FIG. 1B, in the next step, a flip-chip underfill process is performed to form a flip-chip underfill layer 140 to fill up the entirety of the flip-chip undergaps 122, 132.
Referring further to FIG. 1C, in the next step, a molding process is performed by fixing the semi-finished package assembly of FIG. 1B in a molding tool 150 having a mold injection inlet 151. As the semi-finished package assembly of FIG. 1B is fixed in position in the molding tool 150, a molding material 160, such as epoxy resin, is injected through the mold injection inlet 151 into the molding tool 150 until the molding material 160 substantially fills up all the void spaces in the molding tool 150.
Referring further to FIG. 1D, through the forgoing molding process, an encapsulation body 170 is formed to encapsulate all the semiconductor chips 110, 120, 130 over the circuited substrate 100. After this, a ball-implantation process is performed to implant an array of solder balls (i.e., ball grid array) 180 over the back surface 100b of the circuited substrate 100. This completes the fabrication of the multi-chip module by the conventional method.
One drawback to the forgoing conventional method, however, is that, since the flip-chip underfill layer 140 is different in coefficient of thermal expansion (CTE) from the encapsulation body 170, it would easily cause the breaking of the bonding wires 111 during subsequent TCT (Temperature Cycle Test) or TST (Thermal Shock Test) testing procedures.
Some related patents are listed in the following:
U.S. Pat. No. 6,038,136 xe2x80x9cCHIP PACAKGE WITH MOLDED UNDERFILLxe2x80x9d;
U.S. Pat. No. 5,923,090 xe2x80x9cMICROELECTRONIC PACAKGE AND FABRIATION THEREOFxe2x80x9d;
U.S. Pat. No. 5,892,289 xe2x80x9cBARE CHIP MOUNTING STRUCTURE AND MANUFACTURING METHOD THEREFORxe2x80x9d;
U.S. Pat. No. 5,646,828 xe2x80x9cTHIN PACKAGING OF MULTI-CHIP MODULES WITH ENHANCED THERMAL POWER MANAGEMENTxe2x80x9d;
U.S. Pat. No. 5,608,262 xe2x80x9cPACKAGING MULTI-CHIP MODULES WITHOUT WIRE-BOND INTERCONNECTIONxe2x80x9d.
The U.S. Pat. No. 6,038,136 teaches the provision of a vent hole in the substrate to help the molding material to fill freely into the flip-chip undergaps to form a molded underfill layer. One drawback to this patent, however, is that the drilling of a vent hole in the substrate of each package unit would make the overall packaging process more complex in procedural steps. The U.S. Pat. No. 5,923,090, No. 5,892,289, No. 5,646,828, and No. 5,608,262 disclose various types of COC technologies. However, none of them teach a cost-effective solution to the problem of molded underfill.
It is therefore an objective of this invention to provide a new semiconductor packaging technology for fabrication of COC-based multi-chip module with molded underfill, which can help prevent the bonding wires from breaking during TCT or TST testing procedures.
In accordance with the foregoing and other objectives, the invention proposes a new semiconductor packaging technology for fabrication of COC-based multi-chip module.
The new semiconductor packaging technology according to the invention is characterized by the provision of a side gap of an empirically-predetermined width between the overlying chips mounted through COC technology over an underlying chip to serve as an air vent which allows the injected molding material to fill freely into the flip-chip undergaps during molding process.
Fundamentally, the underfill effect is related to a number of factors, including the flowability of the molding material, the size of the overlying chips, and the quantity of the solder bumps. Therefore, in actual application, the exact width of the side gap should be determined empirically through experiments.
Based on experimental data, it is found that the width of the side gap should be equal to or less than 0.3 mm (millimeter). The optimal value for the side gap width may be varied for different package specifications. For instance, in the case of the overlying chips being 3.5 mmxc3x971.8 mm in size, it is found that a side gap width of 0.16 mm would allow the optimal underfill effect, i.e., it allows the molding material to substantially fill up all the entirety of the flip-chip undergaps.